Util Extract
The Util Extract core allows the extraction of the trigger signal and restoration of the data signal that was embedded in the data stream by the AXI ADC Trigger.
Files
Name |
Description |
|---|---|
Verilog source for the peripheral. |
Configuration Parameters
Name |
Description |
|---|---|
NUM_OF_CHANNELS |
Number of channels |
DATA_WIDTH |
Data width. It assumes the trigger is in bit (n*16)-1, with n being the channel number |
Interface
Name |
Description |
|---|---|
clk |
Clock input. Should be synchronous to the input and the output data |
data_in |
Input data from the FIFO. Will replace each trigger bit with the sign extended version of the data. It should be data from the output of the variable fifo |
data_in_trigger |
Data from which the trigger is extracted. It should be data from the input of the variable fifo |
data_valid |
Valid for the input data |
data_out |
Data without the embedded trigger |
valid_out |
Valid for the output data |
trigger_out |
Trigger output. Is an logic OR of the triggers from all the channels that are captured simulaneously |
References
HDL IP core at library/util_extract/util_extract.v