CN0363 DMA Sequencer

?cn0363_dma_sequencer IP-XACT not found.Generate it and the documentation:(cd library/cn0363/cn0363_dma_sequencer; make)(cd docs; make html)

The CN0363 Sequencer FPGA Peripheral is part of the CN0363 HDL project and is responsible to sequence the various data channels to the DMA.

Files

Name

Description

library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.v

Verilog source for the peripheral.

library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer_ip.tcl

TCL script to generate the Vivado IP-integrator project for the peripheral.

Interface

Name

Description
clk

Clock - All other signals are synchronous to this clock.
resetn

Synchronous active low reset - Resets the internal state machine of the core.
phase

AXI-Stream slave - Phase data channel.
data

AXI-Stream slave - Sample data channel.
data_filtered

AXI-Stream slave - Filtered sample data channel.
i_q

AXI-Stream slave - Demodulated I/Q sample data channel.
i_q_filtered

AXI-Stream slave - Filtered demodulated I/Q sample data channel.
dma_wr

FIFO Write Interface master - Low-level SPI bus interface that is controlled by peripheral.
overflow

Output - The overflow signal is asserted if a overflow on the DMA interface is detected.
channel_enable

Input - Data channel enable sequencer output enable.
processing_resetn

Output - Reset signal for the processing pipeline

Detailed Description

The CN0363 DMA sequencer core acts as a link between the CN0363 processing pipeline and the connected DMA controller. On one side it accepts data from the processing pipeline and on the other side it sends the data to the DMA controller. The core is only active when the DMA controller signals that it is waiting for data, when it is inactive it also asserts the processing_resetn signal to keep the processing pipeline in reset. Since the DMA is running at a much faster clock than the output data rate from the processing pipeline the different channels are time-division-multiplexed and send one by one to the DMA controller over the dma_wr interface.

When active, the core cycles through the input channels in the following order:

  1. phase (Reference channel)

  2. data (Reference channel)

  3. data_filtered (Reference channel)

  4. i_q, I component (Reference channel)

  5. i_q, Q component (Reference channel)

  6. i_q_filtered, I component (Reference channel)

  7. i_q_filtered, Q component (Reference channel)

  8. phase (Sample channel)

  9. data (Sample channel)

  10. data_filtered (Sample channel)

  11. i_q, I component (Sample channel)

  12. i_q, Q component (Sample channel)

  13. i_q_filtered, I component (Sample channel)

  14. i_q_filtered, Q component (Sample channel)

Each of these has a corresponding bit in the channel_enable and only if the bit is set, the channel is sent to the dma_wr interface, otherwise it is discarded. This allows an application to select which data channels it wants to capture.

Software Support

References