PulSAR ADC PMDZ

Overview

The purpose of this testbench is to validate the serial interface functionality of the projects/pulsar_adc reference design.

The entire HDL documentation can be found here PULSAR-ADC HDL project.

Block design

The testbench block design includes part of the PulSAR ADC HDL reference design, along with VIPs used for clocking, reset, PS and DDR simulations.

Block diagram

Configuration parameters and modes

The following parameters of this project that can be configured:

• CLK_MODE: defines clocking mode of the device’s digital interface: Options: 0 - SPI mode

• NUM_OF_SDIO: defines the number of MOSI lines of the SPI interface: Options: 1 - Interleaved mode

• CAPTURE_ZONE: defines the capture zone of the next sample. There are two capture zones: 1 - from negative edge of the BUSY line until the next CNV positive edge -20ns

• DDR_EN: defines the type of data transfer. In echo and master clock mode the SDI lines can have Single or Double Data Rates. Options: 0 - MISO runs on SDR.

Configuration files

The following configuration file is available:

Configuration mode	Parameters
	CLK_MODE	NUM_OF_SDIO	CAPTURE_ZONE	DDR_EN
cfg1	0	2	1	0

Tests

The following test program file is available:

Test program	Usage
test_program	Tests the serial interface capabilities.

Available configurations & tests combinations

The test program is compatible with the above mentioned configuration.

CPU/Memory interconnect addresses

Below are the CPU/Memory interconnect addresses used in this project:

Instance	Address
spi_pulsar_adc_axi_regmap	0x44A0_0000
axi_pulsar_adc_dma	0x44A3_0000
spi_clkgen	0x44A7_0000
pulsar_adc_trigger_gen	0x44B0_0000

Interrupts

Below are the Programmable Logic interrupts used in this project:

Instance name	HDL
axi_pulsar_adc_dma	13
spi_pulsar_adc	12

Test stimulus

The test program is structured into several tests as follows:

Environment bringup

The steps of the environment bringup are:

• Create the environment

• Start the environment

• Start the clocks

• Assert the resets

Sanity test

This test is used to check the communication with the AXI REGMAP module of the PulSAR ADC SPI Engine interface, by reading the core VERSION register, along with writing and reading the SCRATCH register.

FIFO SPI test

The FIFO SPI test verifies the simple serial transfers, made through the Execution module.

The steps of this test are:

• Start the SPI clock generator (axi_clkgen)

• Configure the conversion signal generator (axi_pwmgen)

• Enable SPI Engine & configure the Execution module

• Set up the interrupts

• Generate a FIFO transaction

• Capture and compare the results, using the PEEK register of the AXI SPI Engine

Offload SPI test

The Offload SPI test verifies the Offload module functionality.

The steps of this test are:

• Configure the DMA

• Configure the Offload module

• Start the Offload module

• Capture and compare the Offload SDI data

Stop the environment

• Stop the clocks

Building the testbench

The testbench is built upon ADI’s generic HDL reference design framework. ADI does not distribute compiled files of these projects so they must be built from the sources available here and here, with the specified hierarchy described Set up the Testbenches repository. To get the source you must clone the HDL repository, and then build the project as follows:.

Linux/Cygwin/WSL

Example 1

Build all the possible combinations of tests and configurations, using only the command line.

user@analog:~$

cd testbenches/project/pulsar_adc_pmdz

user@analog:~/testbenches/project/pulsar_adc_pmdz$

make

Example 2

Build all the possible combinations of tests and configurations, using the Vivado GUI. This command will launch Vivado, will run the simulation and display the waveforms.

user@analog:~$

cd testbenches/project/pulsar_adc_pmdz

user@analog:~/testbenches/project/pulsar_adc_pmdz$

make MODE=gui

Example 3

Build a particular combination of test and configuration, using the Vivado GUI. This command will launch Vivado, will run the simulation and display the waveforms.

user@analog:~$

cd testbenches/project/pulsar_adc_pmdz

user@analog:~/testbenches/project/pulsar_adc_pmdz$

make MODE=gui CFG=cfg1 TST=test_program

The built projects can be found in the runs folder, where each configuration specific build has it’s own folder named after the configuration file’s name. Example: if the following command was run for a single configuration in the clean folder (no runs folder available):

make CFG=cfg1

Then the subfolder under runs name will be:

cfg1

Resources

HDL related dependencies forming the DUT

IP name	Source code link	Documentation link
AXI_CLKGEN	library/axi_clkgen	AXI CLK Generator
AXI_DMAC	library/axi_dmac	AXI DMAC
AXI_HDMI_TX	library/axi_hdmi_tx *	AXI HDMI TX
AXI_I2S_ADI	library/axi_i2s_adi *	—
AXI_PWM_GEN	library/axi_pwm_gen	AXI PWM Generator
AXI_SPDIF_TX	library/axi_spdif_tx *	—
AXI_SYSID	library/axi_sysid	AXI System ID
AXI_SPI_ENGINE	library/spi_engine/axi_spi_engine	AXI SPI Engine Module
SPI_ENGINE_EXECUTION	library/spi_engine/spi_engine_execution	SPI Engine Execution Module
SPI_ENGINE_INTERCONNECT	library/spi_engine/spi_engine_interconnect	SPI Engine Interconnect Module
SPI_ENGINE_OFFLOAD	library/spi_engine/spi_engine_offload	SPI Engine Offload Module
SYSID_ROM	library/sysid_rom	AXI System ID
UTIL_I2C_MIXER	library/util_i2c_mixer *	—

Legend

* instantiated only for AD40xx/ADAQ40xx

• —

Testbenches related dependencies

Common with most testbenches:

SV dependency name	Source code link	Documentation link
IRQ_HANDLER	library/utilities/irq_handler_pkg.sv	—
LOGGER_PKG	library/utilities/logger_pkg.sv	—
M_AXI_SEQUENCER	library/vip/amd/axi/m_axi_sequencer.sv	—
REG_ACCESSOR	library/regmaps/reg_accessor.sv	—
S_AXI_SEQUENCER	library/vip/amd/axi/s_axi_sequencer.sv	—
TEST_HARNESS_ENV	library/utilities/test_harness_env.sv	Test Harness
UTILS	library/utilities/utils.svh	—
WATCHDOG	library/drivers/common/watchdog.sv	Watchdog

Testbench specific dependencies:

SV dependency name	Source code link	Documentation link
ADI_REGMAP_CLKGEN_PKG	library/regmaps/adi_regmap_clkgen_pkg.sv	—
ADI_REGMAP_DMAC_PKG	library/regmaps/adi_regmap_dmac_pkg.sv	—
ADI_REGMAP_PKG	library/regmaps/adi_regmap_pkg.sv	—
ADI_REGMAP_PWM_GEN_PKG	library/regmaps/adi_regmap_pwm_gen_pkg.sv	—
ADI_REGMAP_SPI_ENGINE_PKG	library/regmaps/adi_regmap_spi_engine_pkg.sv	—
DMA_TRANS	library/drivers/dmac/dma_trans.sv	—
DMAC_API	library/drivers/dmac/dmac_api.sv	—
M_AXIS_SEQUENCER	library/vip/amd/axis/m_axis_sequencer.sv	—
S_AXIS_SEQUENCER	library/vip/amd/axis/s_axis_sequencer.sv	—

More information

• ADI Testbenches User guide

Support

Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.

It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.