common_data.c File Reference

Defines common data to be used by the ad9088 examples. More...

#include "common_data.h"

Include dependency graph for common_data.c:

Functions
int	ad9088_mcs_ops_bind (struct adf4030_dev *adf4030, struct adf4382_dev *adf4382)
	Hand the AD9088 the clock chips its MCS calibration drives.

Variables
struct no_os_uart_init_param	platform_uart_ip
struct adf4382_init_param	adf4382_ip
struct hmc7044_init_param	hmc7044_ip
struct adf4030_init_param	adf4030_ip
struct axi_dmac_init	rx_dmac_ip
struct axi_dmac_init	tx_dmac_ip
struct jesd204_rx_init	rx_jesd204_ip
struct jesd204_tx_init	tx_jesd204_ip
struct adxcvr_init	tx_adxcvr_ip
struct adxcvr_init	rx_adxcvr_ip
struct axi_adc_init	rx_adc_init
struct axi_dac_init	tx_dac_init
struct ad9088_init_param	ad9088_ip

Detailed Description

Defines common data to be used by the ad9088 examples.

Author

CHegbeli (cipri.nosp@m.an.h.nosp@m.egbel.nosp@m.i@an.nosp@m.alog..nosp@m.com)

Copyright 2026(c) Analog Devices, Inc.

SPDX-License-Identifier: BSD-3-Clause

Function Documentation

ad9088_mcs_ops_bind()

int ad9088_mcs_ops_bind	(	struct adf4030_dev *	adf4030,
		struct adf4382_dev *	adf4382 )

Hand the AD9088 the clock chips its MCS calibration drives.

Publishes the accessor tables into ad9088_ip along with the runtime device handles, which do not exist until the chips are probed. Call this after adf4030_init() and adf4382_init(), and before ad9088_init(). Skipping it leaves MCS calibration disabled rather than broken.

Parameters

adf4030	- The BSYNC (SYSREF) provider.
adf4382	- The AD9088 device clock PLL.

Returns

- 0 in case of success, negative error code otherwise.

Variable Documentation

ad9088_ip

struct ad9088_init_param ad9088_ip

Initial value:

= {
    .spi_init = &ad9088_spi_ip,
    .gpio_reset = &gpio_reset_ip,
    .gpio_tri_req = NULL,
    .spi_3wire_en = false,
    .trig_sync_en = false,
    .nyquist_zone = AD9088_NYQUIST_ZONE,
    .subclass = AD9088_JESD_SUBCLASS,
    .jtx0_logical_lane_mapping = AD9088_TX0_LOGICAL_LANE_MAPPING,
    .jtx1_logical_lane_mapping = AD9088_TX1_LOGICAL_LANE_MAPPING,
    .jrx0_physical_lane_mapping = AD9088_RX0_PHYSICAL_LANE_MAPPING,
    .jrx1_physical_lane_mapping = AD9088_RX1_PHYSICAL_LANE_MAPPING,
    .jtx_ser_amplitude = ADI_APOLLO_JESD_DRIVE_SWING_VTT_100,
    .jtx_ser_pre_emphasis = ADI_APOLLO_JESD_PRE_TAP_LEVEL_6_DB,
    .jtx_ser_post_emphasis = ADI_APOLLO_JESD_POST_TAP_LEVEL_3_DB,
    
    .mcs_track_decimation = 0,  
    .mcs_track_win = 0,     
    
    .aion_background_serial_alignment_en = false,
}

adf4030_ip

struct adf4030_init_param adf4030_ip

Initial value:

= {
    .spi_init = &adf4030_spi_ip,
    .spi_4wire_en = false,      
    .cmos_3v3 = false,
    .ref_freq = ADF4030_REF_FREQ_HZ,
    .vco_freq = ADF4030_VCO_FREQ_HZ,
    .bsync_freq = AD9088_SYSREF_CLK_HZ,
    .ref_div = 1,
    .chip_addr = 0,
    
    .alignment_threshold_fs = 1400,
    .alignment_iter = 8,
    .num_channels = NO_OS_ARRAY_SIZE(adf4030_chans),
    .channels = adf4030_chans,
}

adf4382_ip

struct adf4382_init_param adf4382_ip

Initial value:

= {
    .spi_init = &adf4382_spi_ip,
    .spi_3wire_en = true, 
    .cmos_3v3 = false,
    .ref_freq_hz = 125000000,
    .freq = 20000000000,
    .ref_doubler_en = 0,
    .ref_div = 1,
    .cp_i = 15,
    .bleed_word = 0,
    .ld_count = 10,
    .id = ID_ADF4382A,
}

hmc7044_ip

struct hmc7044_init_param hmc7044_ip

Initial value:

= {
    .spi_init = &hmc7044_spi_ip,
    .clkin_freq = {125000000, 125000000, 125000000, 125000000},
    .vcxo_freq = 125000000,
    .pll2_freq = 2500000000,
    .pll1_loop_bw = 200,
    .sysref_timer_div = 1024,
    .in_buf_mode = {0x07, 0x07, 0x00, 0x00, 0x5},
    .gpi_ctrl = {0x00, 0x00, 0x00, 0x00},
    .gpo_ctrl = {0x37, 0x33, 0x00, 0x00},
    .num_channels = NO_OS_ARRAY_SIZE(hmc7044_chans),
    .pll1_ref_prio_ctrl = 0xE1,
    .pll1_ref_autorevert_en = true,
    .sync_pin_mode = 0x1,
    .high_performance_mode_clock_dist_en = false,
    .pulse_gen_mode = HMC7044_PULSE_GEN_CONT_PULSE,
    .channels = hmc7044_chans
}

platform_uart_ip

struct no_os_uart_init_param platform_uart_ip

Initial value:

= {
    .device_id = UART_DEVICE_ID,
    .irq_id = UART_IRQ_ID,
    .asynchronous_rx = true,
    .baud_rate = UART_BAUDRATE,
    .size = NO_OS_UART_CS_8,
    .parity = NO_OS_UART_PAR_NO,
    .stop = NO_OS_UART_STOP_1_BIT,
    .extra = UART_EXTRA,
    .platform_ops = UART_OPS,
}

rx_adc_init

struct axi_adc_init rx_adc_init

Initial value:

= {
    .name = "rx_adc",
    .base = RX_CORE_BASEADDR,
    .num_channels = 0,
}

rx_adxcvr_ip

struct adxcvr_init rx_adxcvr_ip

Initial value:

= {
    .name = "rx_adxcvr",
    .base = RX_XCVR_BASEADDR,
    .sys_clk_sel = ADXCVR_SYS_CLK_QPLL0,
    .out_clk_sel = ADXCVR_PROGDIV_CLK,
    .lpm_enable = 1,
    .lane_rate_khz = AD9088_LANE_RATE_KHZ,
    .ref_rate_khz = 312500,
    .export_no_os_clk = true,
}

rx_dmac_ip

struct axi_dmac_init rx_dmac_ip

Initial value:

= {
    .name = "rx_dmac",
    .base = RX_DMA_BASEADDR,
    .irq_option = IRQ_DISABLED
}

rx_jesd204_ip

struct jesd204_rx_init rx_jesd204_ip

Initial value:

= {
    .name = "rx_jesd",
    .base = RX_JESD_BASEADDR,
    .device_clk_khz = AD9088_DEVICE_CLK_KHZ,
    .lane_clk_khz = AD9088_LANE_RATE_KHZ
}

tx_adxcvr_ip

struct adxcvr_init tx_adxcvr_ip

Initial value:

= {
    .name = "tx_adxcvr",
    .base = TX_XCVR_BASEADDR,
    .sys_clk_sel = ADXCVR_SYS_CLK_QPLL0,
    .out_clk_sel = ADXCVR_PROGDIV_CLK,
    .lpm_enable = 0,
    .lane_rate_khz = AD9088_LANE_RATE_KHZ,
    .ref_rate_khz = 312500,
    .export_no_os_clk = true,
}

tx_dac_init

struct axi_dac_init tx_dac_init

Initial value:

= {
    .name = "tx_dac",
    .base = TX_CORE_BASEADDR,
    .num_channels = 0,
}

tx_dmac_ip

struct axi_dmac_init tx_dmac_ip

Initial value:

= {
    .name = "tx_dmac",
    .base = TX_DMA_BASEADDR,
    .irq_option = IRQ_DISABLED
}

tx_jesd204_ip

struct jesd204_tx_init tx_jesd204_ip

Initial value:

= {
    .name = "tx_jesd",
    .base = TX_JESD_BASEADDR,
    .device_clk_khz = AD9088_DEVICE_CLK_KHZ,
    .lane_clk_khz = AD9088_LANE_RATE_KHZ
}