Shared bring-up (clocks + JESD204) for the AD9082 VPK180 project. More...

#include "common_data.h"
#include "parameters.h"
#include "no_os_error.h"
#include "no_os_spi.h"
#include "xilinx_spi.h"
#include "no_os_gpio.h"
#include "xilinx_gpio.h"
#include "jesd204_clk.h"
#include "no_os_delay.h"
#include "no_os_print_log.h"

Include dependency graph for common_data.c:

Functions
int32_t	app_clock_init (struct no_os_clk dev_refclk[MULTIDEVICE_INSTANCE_COUNT])
	Configure the on-board HMC7044 and export the MxFE device clock.

int32_t	app_jesd_init (struct no_os_clk clk[2], uint32_t reference_clk_khz, uint32_t rx_device_clk_khz, uint32_t tx_device_clk_khz, uint32_t rx_lane_clk_khz, uint32_t tx_lane_clk_khz)
	Bring up the AXI-JESD204 RX/TX link cores.

Variables
struct hmc7044_dev *	hmc7044_dev

struct axi_jesd204_rx *	rx_jesd

struct axi_jesd204_tx *	tx_jesd

Detailed Description

Shared bring-up (clocks + JESD204) for the AD9082 VPK180 project.

Author: Analog Devices, Inc.

SPDX-License-Identifier: BSD-3-Clause

Function Documentation

◆ app_clock_init()

int32_t app_clock_init ( struct no_os_clk dev_refclk[MULTIDEVICE_INSTANCE_COUNT] )

Configure the on-board HMC7044 and export the MxFE device clock.

Application clock setup.

VPK180 / AD9082-FMCA-EBZ: HMC7044 from PLL2 = 3000 MHz. Clock plan and dividers from versal-vpk180-reva-ad9081.dts (the config the PDI was built for: 24.75 Gbps lanes). These MUST match the PDI's GT reference clock, or the GT PLL will not lock (reset-done timeout).

Returns: 0 on success, negative error code otherwise.

◆ app_jesd_init()

int32_t app_jesd_init	(	struct no_os_clk	clk[2],
		uint32_t	reference_clk_khz,
		uint32_t	rx_device_clk_khz,
		uint32_t	tx_device_clk_khz,
		uint32_t	rx_lane_clk_khz,
		uint32_t	tx_lane_clk_khz )

Bring up the AXI-JESD204 RX/TX link cores.

Application JESD setup.

Versal has no ADXCVR: the GT line rate is fixed by the PDI, and only the reset handshake is driven from software over the AXI GPIO. The GT-reset GPIOs are wired into the link FSM; the lane clocks are the fixed jesd204 clocks (no transceiver clock output to chain).

Returns: 0 on success, negative error code otherwise.

Variable Documentation

◆ hmc7044_dev

struct hmc7044_dev* hmc7044_dev

◆ rx_jesd

struct axi_jesd204_rx* rx_jesd

◆ tx_jesd

struct axi_jesd204_tx* tx_jesd

Functions

Variables