#include <axi_jesd204_tx.h>

Public Attributes
const char *	name

uint32_t	base

uint32_t	num_lanes

uint32_t	data_path_width

uint32_t	tpl_data_path_width

struct jesd204_tx_config	config

uint32_t	device_clk_khz

uint32_t	lane_clk_khz

enum jesd204_encoder	encoder

struct no_os_clk_desc *	lane_clk

struct axi_clkgen *	device_clkgen

struct jesd204_dev *	jdev

struct no_os_gpio_desc *	gt_reset_pll

struct no_os_gpio_desc *	gt_reset_dp

struct no_os_gpio_desc *	gt_reset_done

Member Data Documentation

◆ base

uint32_t axi_jesd204_tx::base

Base address

◆ config

struct jesd204_tx_config axi_jesd204_tx::config

Tx coniguration

◆ data_path_width

uint32_t axi_jesd204_tx::data_path_width

Data path width

◆ device_clk_khz

uint32_t axi_jesd204_tx::device_clk_khz

Device Clock in KHz

◆ device_clkgen

struct axi_clkgen* axi_jesd204_tx::device_clkgen

Optional device-clock generator. When set, the link FSM trims it to the per-path device clock (link_rate * data_path_width / tpl_data_path_width), like Linux; NULL leaves it unchanged.

◆ encoder

enum jesd204_encoder axi_jesd204_tx::encoder

Selected Encoder

◆ gt_reset_done

struct no_os_gpio_desc* axi_jesd204_tx::gt_reset_done

◆ gt_reset_dp

struct no_os_gpio_desc* axi_jesd204_tx::gt_reset_dp

◆ gt_reset_pll

struct no_os_gpio_desc* axi_jesd204_tx::gt_reset_pll

Optional GT reset GPIOs (Versal)

◆ jdev

struct jesd204_dev* axi_jesd204_tx::jdev

JESD204 FSM device

◆ lane_clk

struct no_os_clk_desc* axi_jesd204_tx::lane_clk

Lane Clock

◆ lane_clk_khz

uint32_t axi_jesd204_tx::lane_clk_khz

Lane Clock in KHz

◆ name

const char* axi_jesd204_tx::name

Device Name

◆ num_lanes

uint32_t axi_jesd204_tx::num_lanes

Number of lanes

◆ tpl_data_path_width

uint32_t axi_jesd204_tx::tpl_data_path_width

TPL data path width

The documentation for this struct was generated from the following file:

/home/runner/work/no-OS/no-OS/drivers/axi_core/jesd204/axi_jesd204_tx.h

Public Attributes