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no-OS
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no-OS
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Pin map and options for a bit-banged SPI bus, passed via no_os_spi_init_param.extra. More...
#include <maxim_gpio_spi.h>
Public Attributes | |
| uint8_t | port |
| uint8_t | sclk_pin |
| uint8_t | mosi_pin |
| uint8_t | miso_pin |
| uint8_t | cs_pin |
| bool | vddioh |
| uint32_t | half_period_nops |
Pin map and options for a bit-banged SPI bus, passed via no_os_spi_init_param.extra.
All four signal pins live on a single GPIO port (the MAX78000 SPI-capable pins broken out on the FTHR headers are all on port 0). SCLK/MOSI/MISO are the shared bus; cs_pin is THIS device's chip-select, owned exclusively by the core that instantiates the driver. To share one physical bus between two cores, give each core its own descriptor with the same SCLK/MOSI/MISO and a distinct cs_pin, and serialize transfers with an external lock (see max_gpio_spi_ops bus-ownership contract below).
| uint8_t max_gpio_spi_init_param::cs_pin |
Bit position of this device's chip-select pin.
| uint32_t max_gpio_spi_init_param::half_period_nops |
Delay-loop iterations per SCLK phase; three phases make one bit. When 0, it is estimated from no_os_spi_init_param.max_speed_hz and the current core clock (SCLK is then at or below max_speed_hz, approximately). When both are 0, SCLK runs as fast as the loop allows. A non-zero value overrides max_speed_hz.
| uint8_t max_gpio_spi_init_param::miso_pin |
Bit position of the shared master-in pin.
| uint8_t max_gpio_spi_init_param::mosi_pin |
Bit position of the shared master-out pin.
| uint8_t max_gpio_spi_init_param::port |
GPIO port index for all pins (e.g. 0 for MXC_GPIO0).
| uint8_t max_gpio_spi_init_param::sclk_pin |
Bit position (0..31) of the shared serial clock pin.
| bool max_gpio_spi_init_param::vddioh |
Drive/receive at VDDIOH (3.3 V) instead of the reset-default VDDIO (1.8 V). Required when the peripheral is powered from the 3.3 V rail, otherwise driven highs and sampled inputs use the wrong reference.